The present invention generally pertains to electronic circuits that combine MOS and bipolar transistors and is particularly directed to an improvement in a TTL-level-output interface circuit.
For some electronic circuit, high-density MOS transistors for performing multiple logic functions are combined with low-density bipolar transistors for providing output signals at a TTL level in order to provide adequate power for an interfaced circuit load to which power is provided in accordance with said logic functions. TTL-output-level interface circuits that combine MOS and bipolar transistors are described by Nakashiba et al., "A Subnanosecond Bi-CMOS Gate-Array Family", IEEE 1986 Custom Integrated Circuits Conference, pp. 63-66; Nishio, Ogiye and Kadono, "Applications of Hi-BiCMOS Technology", Hitachi Review, Vol 35 (1986), No. 5, pp. 225-230; "How Motorola Moved BiMOS up to VLSI Levels", Electronics, July 10, 1986, pp. 67-70; Lin and Spehn, "Fast, low-power logic array unites CMOS and bipolar", Electronic Design, Apr. 16, 1987; Abramowitz, Kinzer and Tam, "Power-cell library brings high voltage to semicustom ICs", Electronic Design, June 11, 1987, pp. 93-100; "TI's BiCMOS bus interface ICs slash standby current", Electronic Products, June 15, 1987, pp. 17 and 19; and Cohen "NEC's BiCMOS Arrays Shatter Record", Electronics, Aug. 6, 1987, pp. 82-83.
The Nakashiba et al. TTL-level-output interface circuit is described with reference to FIG. 1. This circuit includes a first CMOS inverter 10, a second CMOS inverter, 12, a first npn transistor 14, a second npn transistor 16, a p-channel MOSFET 18, a first n-channel MOSFET 20, a second n-channel MOSFET 22, a third npn transistor 24, a first resistance 26, a second resistance 27, a third resistance 28, an n.phi. network 30, a first diode 32, a second diode 33 and a third diode 34. The n.phi. network 30 includes a fourth npn transistor 36, a fourth resistance 38 and a fifth resistance 40, with the fourth resistance 38 being coupled between the base and the emitter of the fourth third npn transistor 36, and with the fifth resistance 40 being connected between the collector and the base of the fourth npn transistor 36.
The first inverter 10 and the second inverter 12 are each coupled between a voltage supply terminal 42 and a circuit ground terminal 43, and have a common inverter input terminal 44.
The first npn transistor 14 is coupled between the voltage supply terminal 42 and a TTL interface terminal 46 by the resistance 27 and the diode 33 respectively; and the second npn transistor 16 is connected in series with the first npn transistor 14 between the TTL interface terminal 46 and the ground terminal 43.
The first npn transistor 14 has its base coupled to the output terminal 48 of the second inverter 12 for enabling the first npn transistor 14 to conduct current between the voltage supply terminal 42 and the TTL interface terminal 46 when a low input signal is applied at the inverter input terminal 44, and for clamping the first npn transistor 14 in a non-conductive state when a high input signal is applied at the inverter input terminal 44.
The second npn transistor 16 has its base 50 coupled to the ground terminal 43 through the second n-channel MOSFET 22 that has its gate coupled to the output terminal 49 of the first inverter 10 for clamping the second npn transistor 16 in a nonconductive state when a low input signal is applied at the inverter input terminal 44.
The second npn transistor 16 also has its base coupled to the voltage supply terminal 42 via the third npn transistor 24, which in turn has its base connected to the voltage supply terminal 42 by the first resistance 26 and the p-channel MOSFET 18. The p-channel MOSFET 18 has its gate connected to the inverter input terminal 44 so that the third npn transistor 24 is rendered conductive for enabling the second npn transistor 16 to conduct current from the TTL interface terminal 46 to the ground terminal 43 when a high input signal is applied at the inverter input terminal 44. The base of the third npn transistor 24 is biased above circuit ground by the third resistance 28. The second n-channel MOSFET is connected between the base of the third npn transistor 24 and the ground terminal 43, and has its gate connected to the output of the first inverter 10 for clamping the base of the third npn transistor 14 to circuit ground when a high input signal is applied at the inverter input terminal 44.
The fourth npn transistor 36 of the n.phi. network 30 has its emitter coupled to the TTL output terminal 46 by the third diode 34 and its collector 51 coupled to the base of the third npn transistor 24 for limiting the base current of the second npn transistor 16 in order to prevent saturation of the second npn transistor 16.
In an operating n.phi. network, such as network 30, because the base current is negligible, V.sub.c =V.sub.e +n.phi., wherein .phi.=V.sub.b -V.sub.e ; V.sub.b, V.sub.c and V.sub.e are the base voltage, the collector voltage and the emitter voltage of the transistor 36; n=(1+R.sub.2 /R.sub.1); R.sub.1 is the resistance 40 connected between the base and emitter of the transistor 36; and R.sub.2 is the resistance 38 connected between the base and the collector of the transistor 36. Because V.sub.c of the network transistor 36 is always n.phi. greater than V.sub.e, by coupling the emitter of the network transistor 36 to the collector of the second npn transistor 16 and the collector of the network transistor 36 to the base of the second npn transistor 16, and by choosing the values of the resistances R.sub.1 and R.sub.2 such that n=1.5, when V.sub.c of the network transistor 36 is maintained at 3.phi. (approximately 2.1 volts), the collector-to-base voltage of the second npn transistor 16 is maintained at 0.5.phi. (approximately 0.35 volts) and thereby prevents saturation of the second npn transistor 16, which would occur if the base-to-collector voltage of the second npn transistor 16 reached or exceeded 0.4 volts.